2.2 The MOS Capacitor

To understand the MOSFET, it is convenient to analyze the MOS capacitor first, which
constitutes the important gatechannelsubstrate structure of the MOSFET. The MOS
capacitor is a two terminal semiconductor device of practical interest in its own right. As
indicated in figure 2.2, it consists of a metal contact separated from the semiconductor
substrate. Almost universally, the MOS structure utilizes doped silicon as the substrate
and its native oxide, SiO2, as the insulator. In the siliconsilicon dioxide system, the
density of surface states at the oxidesemiconductor interface is very low compared to the
typical channel carrier density in a MOSFET. Also, the insulating quality of the oxide is

quite good.












We assume that the insulator layer has infinite resistance, preventing any charge carrier
transport across the dielectric layer when a bias voltage is applied between the metal and
semiconductor. Instead, the applied voltage will induce charges and counter charges in
the metal and in the interface layer of the semiconductor, similar to what is expected in
the metal plates of a conventional parallel plate capacitor. However, in the MOS
capacitor we may use the applied voltage to control the type of interface charge we
induce in the semiconductor – majority carriers, minority carriers and depletion region.


Indeed, the ability to induce and modulate a conducting sheet of minority careers at the
semiconductor – oxide interface is the basis of the operation of the MOSFET.


2.2.1 Interface Charge
The induced interface charge in the MOS capacitor is closely linked to the shape of the
electron energy bands of the semiconductor near the interface. At zero applied voltage,
the bending of the energy bands are ideally determined by the difference in the work
functions of the metal and the semiconductor. This band bending changes with the
applied bias and the bands become flat when we apply the socalled flatband voltage
given by

where Fm and FS are the work functions of the metal and the semiconductor,
respectively, XS is the electron affinity for the semiconductor, Ec is the energy of the
conduction band edge and EF is the Fermi level at zero applied voltage. The various
energies involved are indicated in figure 2.3, where we show typical band diagrams of
    MOS capacitor at zero bias and with the voltage V=VFB applied to the metal contact
    relative to the semiconductoroxide interface.


    At stationary conditions, no net current flows in the direction perpendicular to the
    interface owing to the very high resistance of the insulator layer. Hence, the Fermi level
    will remain constant inside the semiconductor, independent of the biasing conditions.
    However, between the semiconductor and the metal contact, the Fermi level is shifted by
    EFM – EFS = qV (see Figure 2.3(b)). Hence, we have a quasiequilibrium
    situation in which the semiconductor can be treated as if in thermal equilibrium.


A MOS structure with a ptype semiconductor will enter the accumulation regime of
operation when the voltage applied between the metal and the semiconductor is more

negative than the flatband voltage (VFB < 0 in Figure 2.3). In the opposite case, when
V > VFB, the semiconductoroxide interface first becomes depleted of holes and we enter
the socalled depletion regime.

By increasing the applied voltage, the band bending becomes so large that the energy
difference between the Fermi level and the bottom of the conduction band at the
insulatorsemiconductor interface becomes smaller than that between the Fermi level and
the top of the valance band. This is the case indicated for V = 0V in Figure 2.3 (a).
Carrier statistics tells us that the electron concentration then will exceed the hole
concentration near the interface and we enter the inversion regime. At still larger applied
voltage, we finally arrive at a significant conducting sheet of inversion charge at the
interface.


The symbol y is used to signify the potential in the semiconductor measured relative to
the potential at a position x deep inside the semiconductor. To note that y becomes
positive when the bands bend down, as in the example of a ptype semiconductor shown
in Figure 2.4.

from equilibrium statistics, we find that the intrinsic Fermi level Ei in the bulk
corresponds to an energy separation qjb from the actual Fermi level EF of the doped
semiconductor,

          where Vth is the thermal voltage, Na is the shallow acceptor density in the ptype
semiconductor and ni is the intrinsic carrier density of silicon. According to the usual
definition, strong inversion is reached when the total band bending equals 2qjb,
corresponding to the surface potential y s = 2jb. Values of the surface potential such that
0 < y s < 2jb correspond to the depletion and the weak inversion regimes, y
s = 0 is the flatband condition, and y s < 0 corresponds to the accumulation mode.