Chapter 2::MOS Device Physics and Operations

MOS Device Physics and Operations

2.1 Introduction

A field effect transistor (FET) operates as a conducting semiconductor channel with two

ohmic contacts the source and the drain – where the number of charge carriers in the

channel is controlled by a third contact – the gate. In the vertical direction, the gatechannel

substrate structure (gate junction) can be regarded as an orthogonal twoterminal device, 

which is either a MOS structure or a reversebiased rectifying device that controls

the mobile charge in the channel by capacitive coupling (field effect). Examples of FETs

based on these principles are MetalOxideSemiconductor FET (MOSFET), junction FET

(JFET), metalsemiconductor FET (MESFET), and heterostructure FET (HFETs). In all

cases, the stationary gatechannel impedance is very large at normal operating conditions.

The basic FET structure is shown schematically in figure 2.1.

The most important FET is the MOSFET. In a silicon MOSFET, the gate contact is

separated from the channel by an insulating silicon dioxide (SiO2) layer. The charge

carriers of the conducting channel constitute an inversion charge, that is, electrons in the

case of a ptype substrate (nchannel device) or holes in the case of an ntype

substrate(pchannel device), induced in the semiconductor at the siliconinsulator

interface by the voltage applied to the gate electrode. The electrons enter and exit the 

channel at n + sourceand drain contacts in the case of an nchannelMOSFET, and at 

p+ contacts in the case of a pchannel MOSFET.

MOSFETs are used both as discrete devices and as active elements in digital and analog

monolithic integrated circuits (ICs). In past decade, the device feature size of such

circuits has been scaled down into the deep submicrometer range. Presently, the 0.13mm

technology node for complementary MOSFET (CMOS) is used very large scale Ics.

(VLSIs) and, within a few years, sub0.1mm technology will be available, with a

commensurate increase in speed and in integration scale. Hundreds of millions of

transistors on a single chip are used in microprocessors and in memory ICs today.

CMOS technology combines both nchannel and pchannel MOSFETs to provide very

low power consumption along with high speed. New silicononinsulator (SOI)technology

 may help achieve threedimensional integration, that is, packing of devices

into many layers with a dramatic increase in integration density. New improved device

structures and the combination of bipolar and field effect technologies (BiCMOS) may

lead to further advances, yet unforeseen. One of the rapidly growing areas of CMOS is in

analog circuits, spanning a variety of applications from audio circuits operating at the

kilohertz (kHz) range to modern wireless applications operating at gigahertz (GHz)

frequencies.