2.2.3 MOS Capacitance

2.2.3 MOS Capacitance

In a MOS capacitor, the metal contact and the neutral region in the doped semiconductor

substrate are separated by the insulator layer, the channel, and the depletion region.

Hence, the capacitance Cmos of the MOS structure can be represented as a series

connection of the insulator capacitance i i i C = S e d , where S is the area of the MOS

capacitor, and the capacitance of the active semiconductor layer Cs,

where Qs is the total charge per unit area in the semiconductor and y

s is the surface

potential. Using (2.9) to (2.12) for Qs and performing the differentiation , we obtain

here, s s Dp C = Se L 0 is the semiconductor capacitance at the flatband

condition (i.e., for

ys

=0) and LDp is the Debye length given by (2.11), equation (2.14) describes the

relationship between the surface and the applied bias.

The semiconductor capacitance can formally be represented as the sum of two

capacitancesa depletion layer capacitance, Cd and a free carrier capacitance Cfc. Cfc

together with a series resistance RGR describes the delay caused by thegeneration/

recombination mechanisms in the buildup and removal of inversion charge in

response to changes in the bias voltage. The depletion layer capacitance is given by

                                           d s d C = Se / d

is the depletion layer width. In strong inversion, a change in the applied voltage will

primarily affect the minority carrier charge at the interface, owing to the strong

dependence of this charge on the surface potential. This means that the depletion width

reaches a maximum value with no significant further increase in the depletion charge.

This maximum depletion width ddT can be determined from (2.23) by applying the

threshold condition, y s= 2jb. the corresponding minimum value of the depletion

capacitance is 

                                                CdT = S es / ddT.

As indicated, the variation in the minority carrier charge at the interface comes from the

processes of generation and recombination mechanisms, with the creation and removal of

electronhole pairs. Once an electronhole pair is generated, the majority carrier (a hole in

ptype material and an electron in ntype material) is swept from the space charge region

into the substrate by the electric field of this region. The minority carrier is swept in the

opposite direction toward semiconductorinsulator interface. The variation in the minority

carrier charge in the semiconductorinsulator interface therefore proceeds at a rate limited

by the time constants associated with the generation/recombination processes. This finite

rate represents a delay, which may be represented electrically in terms of an RC product

consisting of the capacitance Cfc and the resistance RGR, as reflected in the equivalent

circuit of the MOS structure shown in figure 2.7. The capacitance Cfc becomes important

in the inversion regime, especially in strong inversion where the mobile charge is

important. The resistance Rs in the equivalent circuit is the series resistance of the neutral

semiconductor layer and the contacts.

The calculated dependence of Cmos on the applied voltage for different frequencies is

shown in figure 2.8. For applied voltages well below threshold, the device is in accumulation

 and Cmos equals Ci. As the voltage approaches threshold, the semiconductor passes the 

flatband condition where Cmos has the value CFB, and then enters the depletion and weak

 inversion regimes where the depletion width increases and the capacitance value drops steadily

 until it reaches the minimum value at threshold given by (2.27). The calculated curves clearly

 demonstrate how the MOS capacitance in the strong inversion regime depends on the frequency, with a value of ¥ mos C at high frequencies to Ci at low frequencies.

We note that in a MOSFET, where the highly doped source and drain regions act as

reservoirs of minority carriers for the inversion layer, the time constant RGRCfc must be

19 substituted by a much smaller time constant corresponding to the time needed for

transporting carriers from these reservoirs in and out of the MOSFET gate area.Consequently,

 highfrequency strong inversion MOSFET gatechannel CV characteristics will resemble the

 zero frequency MOS characteristics.