3.4.2.4 IDS vs. VDS curve (VGS = 2 volt):

3.4.2.4 IDS vs. VDS curve (VGS = 2 volt):

As we see, from the mathematical representation of the alpha powerlaw MOSFET model, the active region current and the saturation region current in IDS vs. VDS curvesand the subthreshold region current and the active region current in the IDS vs. VGS curve are linearly proportional to the determined oxide capacitance of the respective devices. So, the amount of current decreases with the increase of oxide thickness as oxide capacitance is inversely proportional to the oxide thickness.Also, the amount of access of both the devices in the active region in case of IDS vs. VDS curves increase with the increment of applied gate bias voltages. Similarly, the increment of the gate voltage increases also increases the value of the output current IDS (See figure3.2, 3.3, 3.4 & 3.5).

3.4.3 Subthreshold slope

From the representation of the model, we find that, subthreshold current DS SUB I depends

exponentially on gate bias voltage VGS. However, VDS has little influence once VDS

exceeds a few q kT b = . Obviously, we find a linear behaviour in the subthreshold regime

from figure 3.1 when we plot IDS – VGS. The slope of this line (or more precisely the

reciprocal of the slope) is known as the subthreshold slope, S, which has typical value of

~70 mV/decade at room temperature for stateoftheart MOSFETs. This means that a

change in the input VGS of 70 mV will change the output IDS by an order of magnitude.

Clearly, the smaller the value of S, the better the transistor is as a switch. A small value

of S means a small change in the input bias can modulate the output current considerably.

It can be shown that S is expressed by

The elaborated expression gives us an idea of representing the electrical equivalent circuit

of the MOSFET in terms of capacitors. The expression in brackets in the above equation

is simply the capacitor divider ratio that tells what the fraction of the applied gate bias

appears at the Si – SiO2 interface as the surface potential. Ultimately it is the surface

potential that is responsible for modulating the barrier between the source and drain, and

therefore the drain current, IDS. Hence, S is a measure of the efficacy of the gate potential

in modulating IDS. From equation (3.17) we find that S is improved by reducing the gate

oxide thickness, which is reasonable because if the gate electrode is closer to the channel,

the gate control is obviously better. The value of S is higher for heavy channel doping

(which increases the depletion capacitance) or if the silicon – oxide interface has many

fast interface states. In our observations, we obtained the value of S to be 59.9

mV/decade for 3.5 nm devices and 59.4 mV/decade for 2.2 nm devices. So, we find that

the decrement of the oxide thickness results in a better responsive MOSFET as a switch.