5.6 Changes in Occupancy and Charge State with Gate Bias

5.6 Changes in Occupancy and Charge State with Gate Bias

This section will illustrate the change in occupancy and charge state with different gate

bias voltage. For this section we apply a small DrainSource Voltage (VDS) of 0.1 volt

and ground the source terminal.

5.6.1 Accumulation

When the gate voltage, VG is less than zero, the MOSFET is said to operate in the

Accumulation mode. Holes are drawn to the SiSiO2 interface and no electron flows from

source to drain [8].

Donor type interface states that are above Fermi level of the silicon, EFS, will be empty of

electrons and become positively charged, while those that are below EFS will be filled

with electrons and be neutral [18].

Acceptor type interface states will be above EFS and be empty of electrons thus being

neutral [18]. Figure 5.3: Energyband diagram in a ptype semiconductor showing the charge

trapped in the interface states when the MOSFET gate bias is VG < 0 [18]