4.3 Modification of the alphapower
law model
Our study of the physical alphapower law MOSFET Model includes a modification about MOS capacitance. In thesubthreshold region, the effects of depletion capacitanceand capacitance due to interface trapped charges are not included. As a consequence
revised model is presented with the employment of interface trapped charge capacitance(Cit) and depletion capacitance (Cd). The revised model includes the arrangement of capacitances in the following manner [15]:
Now it comes to a point of determining the different components of the total capacitance(C). Oxide capacitance is varied from the flatband capacitance (CFB) to the intrinsic value of the oxide capacitance (ei/tox). The flatband capacitance is a series combination of Debye capacitance (Cdebye) and insulator capacitance (Ci) [15]. It is assumed that the oxide capacitance (Cox) varies linearly with the application of the gate bias voltage (VGS). In our proposal we determine the gate to substrate voltage (VGS) or the gate bias from surface potentials (fs) by the following equation [14]:
Then we analyzed the interface trap distribution and measured its value to be equal to 65.771 nF (See Chapter 5 for detail). Thus we take interface trapped charge capacitance, Cit = 65.771 nF. Then following the capacitor arrangement of figure 4.2 we measured the
equivalent MOS capacitance (Cmos). The calculated value of the Cmos is then used in the expressions of the various expressions of physical alphapower law MOSFET model in places of Cox. And thus we obtained a quite remarkable deviation in the measured values of the drain current, IDS.
Our study of the physical alphapower law MOSFET Model includes a modification about MOS capacitance. In thesubthreshold region, the effects of depletion capacitanceand capacitance due to interface trapped charges are not included. As a consequence
revised model is presented with the employment of interface trapped charge capacitance(Cit) and depletion capacitance (Cd). The revised model includes the arrangement of capacitances in the following manner [15]:
Now it comes to a point of determining the different components of the total capacitance(C). Oxide capacitance is varied from the flatband capacitance (CFB) to the intrinsic value of the oxide capacitance (ei/tox). The flatband capacitance is a series combination of Debye capacitance (Cdebye) and insulator capacitance (Ci) [15]. It is assumed that the oxide capacitance (Cox) varies linearly with the application of the gate bias voltage (VGS). In our proposal we determine the gate to substrate voltage (VGS) or the gate bias from surface potentials (fs) by the following equation [14]:
Then we analyzed the interface trap distribution and measured its value to be equal to 65.771 nF (See Chapter 5 for detail). Thus we take interface trapped charge capacitance, Cit = 65.771 nF. Then following the capacitor arrangement of figure 4.2 we measured the
equivalent MOS capacitance (Cmos). The calculated value of the Cmos is then used in the expressions of the various expressions of physical alphapower law MOSFET model in places of Cox. And thus we obtained a quite remarkable deviation in the measured values of the drain current, IDS.
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